Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 10 is shown in FIG. 1. The memory cell 10 comprises a semiconductor substrate 12 of a first conductivity type, such as P type. The substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line BL 20 is connected to the second region 16. A word line WL 22 is positioned above a first portion of the channel region 18 and is insulated therefrom. The word line 22 has little or no overlap with the second region 16. A floating gate FG 24 is over another portion of the channel region 18. The floating gate 24 is insulated therefrom, and is adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. The floating gate 24 may overlap the first region 14 to provide coupling from the region 14 into the floating gate 24. A coupling gate CG (also known as control gate) 26 is over the floating gate 24 and is insulated therefrom. An erase gate EG 28 is over the first region 14 and is adjacent to the floating gate 24 and the coupling gate 26 and is insulated therefrom. The top corner of the floating gate 24 may point toward the inside corner of the T-shaped erase gate 28 to enhance erase efficiency. The erase gate 28 is also insulated from the first region 14. The cell 10 is more particularly described in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 28 with other terminals equal to zero volt. Electrons tunnel from the floating gate 24 into the erase gate 28 causing the floating gate 24 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 26, a high voltage on the source line 14, a medium voltage on the erase gate 28, and a programming current on the bit line 20. A portion of electrons flowing across the gap between the word line 22 and the floating gate 24 acquire enough energy to inject into the floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in read condition. The resulting cell programmed state is known as ‘0’ state.
In the prior art, various combinations of positive or zero voltages were applied to word line 22, coupling gate 26, and floating gate 24 to perform read, program, and erase operations. The prior art did not apply negative voltages for these operations.
One object of the present invention is to utilize negative and positive voltages for a non-volatile memory cell device such that a negative voltage is applied to word line 22 and/or coupling gate 26 during read, program, and/or erase operations for selected or unselected cells, depending on the operation. This will allow for the use of a lower positive voltage supply than in the prior art, which will allow for a more compact and space-efficient layout for the memory cell device.